---------------------------------------------------------------------------
-- Company     : Vim Inc
-- Author(s)   : Fabien Marteau
-- 
-- Creation Date : 23/04/2008
-- File          : atmega_wrapper_tb.vhd
--
-- Abstract : Test the wrapper between atmega and wishbone 
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

use work.atmega_pkg.ALL;

---------------------------------------------------------------------------
Entity atmega_wrapper_tb is 
---------------------------------------------------------------------------
end entity;


---------------------------------------------------------------------------
Architecture atmega_wrapper_tb_1 of atmega_wrapper_tb is
	---------------------------------------------------------------------------

	
	CONSTANT HALF_PERIODE : time := 10 ns;  -- Half clock period of 50MHz
	CONSTANT ATMEGA_HALF_PERIODE : time := 31 ns;  -- Half clock period of 50MHz

	component	 atmega_wrapper
		port (
			-- Atmega128 port
			Address_H     : in std_logic_vector( 7 downto 0);
			DA            : inout std_logic_vector( 7 downto 0);
			ALE           : in std_logic ;
			RD            : in std_logic ;
			WR            : in std_logic ;
			DIR_buffer    : out std_logic ;

			-- Wishbone port
			wbm_address   : out std_logic_vector( 15 downto 0);
			wbm_readdata  : in std_logic_vector( 7 downto 0);
			wbm_writedata : out std_logic_vector( 7 downto 0);
			wbm_strobe    : out std_logic ;
			wbm_write     : out std_logic ;
			wbm_ack       : in std_logic ;
			wbm_cycle     : out std_logic ;

			-- clock 50MHz and reset
			clk           : in std_logic ;
			reset_n         : in std_logic 
			);
	end component;

	-- Atmega128 port
	signal  		Address_H     : std_logic_vector( 7 downto 0);
	signal			DA            : std_logic_vector( 7 downto 0);
	signal			ALE           : std_logic ;
	signal			RD            : std_logic ;
	signal			WR            : std_logic ;
	signal			DIR_buffer    :  std_logic ;
	-- Wishbone port
	signal			wbm_address   :  std_logic_vector( 15 downto 0);
	signal			wbm_readdata  : std_logic_vector( 7 downto 0);
	signal			wbm_writedata :  std_logic_vector( 7 downto 0);
	signal			wbm_strobe    :  std_logic ;
	signal			wbm_write     :  std_logic ;
	signal			wbm_ack       : std_logic ;
	signal			wbm_cycle     :  std_logic ;
	-- clock 50MHz areset
	signal			clk           : std_logic ;
	signal			reset_n        : std_logic ;

	signal			atclk : std_logic ;

	signal address : std_logic_vector( 15 downto 0);

begin

	reset_n <= '0', '1' AFTER 4*HALF_PERIODE;
	-- Clock
	Clockp : process
	begin
		clk <= '1';
		wait for HALF_PERIODE;
		clk <= '0';
		wait for HALF_PERIODE;
	end process Clockp;

	AtmegaClk : process
	begin
		atclk <= '1';
		wait for ATMEGA_HALF_PERIODE;
		atclk <= '0';
		wait for ATMEGA_HALF_PERIODE;
	end process AtmegaClk;

	stimulis : process
		variable value : std_logic_vector( 7 downto 0);
	begin
		Address_H  <= (others => '0');
		DA         <= (others => 'Z');
		ALE        <= '0';
		RD         <= '1';
		WR         <= '1';
		wait for 50 ns;
	
		-- Write test
		atmega_write(x"0002",x"08",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	

		-- Read test
		atmega_read(x"0002",value,
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	

		wait for 100 ns;
		assert false report "End of test" severity error;
	end process stimulis;


	connect_atmega_wrapper : atmega_wrapper
	port map (
		-- Atmega128 port
		Address_H     => Address_H ,
		DA            => DA,
		ALE           => ALE,
		RD            => RD,
		WR            => WR,
		DIR_buffer    => DIR_buffer,
		-- Wishbone port
		wbm_address   => wbm_address,
		wbm_readdata  => wbm_readdata,
		wbm_writedata => wbm_writedata,
		wbm_strobe    => wbm_strobe,
		wbm_write     => wbm_write,
		wbm_ack       => wbm_ack,
		wbm_cycle     => wbm_cycle,
		-- clock 50MHz and reset
		clk           => clk,
		reset_n         => reset_n
		);

end architecture atmega_wrapper_tb_1;

